SSRLabs - Licensable IP

We have developed a large number of non-core building blocks and IP that we are interested in selling or licensing. Please contact us for a detailed list of those parts and building blocks.

  • Advanced Scalar Math Functions (our IP blocks are all IEEE 754 floating-point compliant but reduce the number of exceptions and NaNs; integer-only upon request)
  • Advanced Vector Functions
  • Matrix Functions
  • Graph Search Functions
  • Deep Learning Functions
  • Machine Learning Functions
  • General Artifical Intelligence Functions
  • Image processing and analysis Functions
  • Object identification and tracking Functions
  • Universal Host Port (UHP)
  • Universal Host Port (UHP) to DDR3/DDR4 Adapter
  • Hybrid Memory Cube Host Adapter
  • The Hybrid Memory Cube (HMC) base logic is configurable and allows for incremental logic and components to be integrated. Please send us a message if you are interested in buying or licensing this non-core IP. The HMC HA is - as stated on the HMCC Partner page - available in all configurations required by the standard, including the version 2.0 with a 30 GHz symbol rate as a hard macro. We doubt that a synthesizable core will achieve that symbol rate on arbitrary processes as claimed by other suppliers. We also offer an internal interface that can make use of the data rate, and don't choke it by limiting it to a bus interface that we know cannot sustain an appropriate data rate.