Even the most recent memory subsystems (DDR3, DDR4, the upcoming DDR5 and even HBM/HBM2) rely on outdated architectures that work best with single-core, single-processor hosts. As we all know any modern computer deploys multi-core multi-threaded processors, and therefore the old paradigm does not apply any more. Multi-core processors and even more so massively parallel processors are hampered by the design philosophy of current memory subsystems. SSRLabs has identified that weakness and developed a Very Large Capacity Memory that supports all host processors irrespective of how many cores they contain (multiple, many or massively parallel cores) with our Universal Host Port (UHP). All connections are point-to-point connections and not multi-drop buses, and thus they maintain performance with a full-duplex bandwidth of 60 GB/s per channel and port. Currently a 128 GB version and a 512 GB version are in the final stages of development. These memory ASICs are 3D stacked components with a base logic ASIC and the memory modules in multiple stacks. On a footprint of less than 70 mm * 70 mm we can provide 128 or 512 GB of memory at performance levels higher than quad DDR4 channels.
Our Very Large Capacity Memory is based on the idea that the processor does not need a memory controller, and that all memory controllers should reside on the memory module itself. That controller makes the interface to the processor universal and agnostic to the memory type. At the same time we can remove the DRAM Controller from the CPU, offloading its thermal footprint by a few Watts. That power can be used to integrate an HBM2 DRAM Controller for use as an L4 Cache on the CPU substrate.