SSRLabs - Floating-Point Coprocessor

SSRLabs has developed a dedicated floating-point coprocessor to improve a variety of computational tasks in modern servers. We support applications heavy in floating-point requirements for traditional HPC (High Performance Computing) at better performance per Dollar spent - both in capital expenses and in lifetime operating costs - and better energy efficiency than existing solutions. Unlike other processors or accelerators SSRLabs' coprocessors are massively parallel coprocessors that will automatically share and distribute the computational load. They are not MIMD or SIMD engines and therefore do not require the programmer to make assumptions about the setup of the target system.

These coprocessors outperform Intel's Xeon Phi, GPGPUs, IBM's Cell Broadband Engine (CBE) and its POWER8+ and all FPGA-based solutions. Their memory and I/O bandwidth vastly exceeds that of other processors or coprocessors. Unlike those other processors or coprocessors ours have the memory and I/O bandwidth to support our performance claims. Our accelerators scale out better than others due to a novel I/O subsystem that supplants QPI and is higher bandwidth than Gen-Z. We call this interface UHP for Universal Host Port as it connects processors to processors, accelerators and to our memory ASIC, the vlcRAM. On top of that, they are easier to program. Load-balancing is performed automatically.

These comprehensive subsystems include dedicated coprocessors, firmware, software and APIs as well as SDK plugins. An openCL API is available for the floating-point coprocessor. Please contact us for a list of supported APIs if openCL is not feasible for your application.