For demonstration purposes and for customers who have a need for massive additional floating-point performance or graph search applications we have started the development of a rackable 6U 19" Accelerator Appliance that can be connected to one or more standard servers. Applications include FEA/FEM, CFD, simulations, forecasts and financial modeling. This appliance can also be used for simulation of and solving any n-body-problem, including protein folding and other biomedical simulations, and multi-dimensional field solvers for scalars and vectors. It makes use of the massively parallel floating-point engines inside the floating-point coprocessors. This Accelerator Appliance can be equipped with up to four boards with up to 4 coprocessors each and up to 16 of our Very Large Capacity Memory ASICs per board. The Accelerator Appliance can be connected to 4 to 20 hosts, depending on the specific configuration. SSRLabs will provide the Accelerator Appliance in a 19" rackable enclosure in user-selectable configurations based on customer's specifications. This appliance will work with our floating-point coprocessor. We cannot disclose final performance and power numbers or total memory capacity or bandwidth yet. Memory capacity is at least 16 TB for the appliance, and the addressing scheme foresees over 128000 coprocessor boards with 256 TB memory each. Compare that to Intel's Physical Address Extension (PAE) on x86-64 with 36 or now up to 46 address bits (64 TB address space). In other words, our Accelerator Appliances can address each other and each others' memory even if the hosts' CPU has lost its overview. The Accelerator Appliance uses our own very large capacity Memory ASIC for unrivaled performance particularly in Big Data applications.